The present invention relates generally to semiconductor device processing, and, more particularly, to a method for reactive ion etch processing of dual damascene structures formed in porous dielectric materials.
In the fabrication of integrated circuit devices, it is often desirable to isolate individual components of the integrated circuits from one another with insulative materials. Such insulative materials may include, for example, silicon dioxide, silicon nitride and silicon carbide. While these materials may have acceptable insulating properties in many applications, they also have relatively high dielectric constants, which can lead to capacitive coupling between proximate conductive elements. This is particularly disadvantageous, given the ever-decreasing distances between conductive circuit elements, and the use of multi-layered structures. An unnecessary capacitive coupling between adjacent wires increases the RC time delay of a signal propagated therethrough, resulting in decreased device performance.
Thus, for specific applications, insulating materials having relatively low dielectric constants (e.g., k<3) are desired. In very large scale integrated circuit (VLSI) technology, silicon dioxide (SiO2) has been traditionally used as an interlevel dielectric (ILD) material in conjunction with aluminum interconnect material. More recently, however, significant advancements have been made to enhance circuit performance by replacing the SiO2 with a “low-k” dielectric and by using copper (higher conductivity) interconnect.
Organic materials or materials of low density used as low-k dielectrics are frequently etched when the resist is stripped from the wafer. This results in vias being etched too deeply or completely etched to a sub-film before the resist is removed. To overcome this drawback, a dual damascene reactive ion etch (RIE) process is split into two discrete steps where the vias are etched first, followed by the trench definition. The reverse of this process is also used, wherein the trench pattern is etched prior to the vias. In either case, however, stripping of the resist presents problems of depth and profile control.
Furthermore, organosilciate (OSG) type materials used as dielectrics are sensitive to wet cleaning steps, such as a dilute hydrofluoric acid (DHF) rinse. For example, a porous OSG film has been shown to etch in DHF solutions. In addition, the absorption of liquid matter in the pores of the dielectric can pose a major problem to the liner integrity. Accordingly, it would be desirable to be able to implement a damage free etch process that isolates the dielectric layer from resist stripping steps, while also controlling etch rate of the dielectric layer and maintaining a robust processing window.